A word or acronym used in assembly language to represent a binary machine instruction operation code. Different processors have different instruction sets and therefore use a different set of mnemonics to represent them.
E.g. ADD, B (branch), BLT (branch if less than), SVC, MOVE, LDR (load register).
- Instruction prefetch
architecture A technique which attempts to minimise the time a processor spends waiting for instructions to be fetched from memory. Instructions following the one currently being executed are loaded into a prefetch queue when the processor’s external bus is otherwise idle. If the processor executes a branch instruction or receives an interrupt then the queue […]
[in-struhk-shuh n] /ɪnˈstrʌk ʃən/ noun 1. the act or practice of or teaching; education. 2. knowledge or information imparted. 3. an item of such knowledge or information. 4. Usually, instructions. orders or directions: The instructions are on the back of the box. 5. the act of furnishing with authoritative directions. 6. Computers. a command given […]
- Instruction scheduling
The compiler phase that orders instructions on a pipelined, superscalar, or VLIW architecture so as to maximise the number of function units operating in parallel and to minimise the time they spend waiting for each other. Examples are filling a delay slot; interspersing floating-point instructions with integer instructions to keep both units operating; making adjacent […]
- Instruction set
architecture The collection of machine language instructions that a particular processor understands. The term is almost synonymous with “instruction set architecture” since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate. (1999-07-05)