A technique which attempts to minimise the time a processor spends waiting for instructions to be fetched from memory. Instructions following the one currently being executed are loaded into a prefetch queue when the processor’s external bus is otherwise idle. If the processor executes a branch instruction or receives an interrupt then the queue must be flushed and reloaded from the new address.
Instruction prefetch is often combined with pipelining in an attempt to keep the pipeline busy.
By 1995 most processors used prefetching, e.g. Motorola 680×0, Intel 80×86.
[First processors using prefetch?]
[in-struhk-shuh n] /ɪnˈstrʌk ʃən/ noun 1. the act or practice of or teaching; education. 2. knowledge or information imparted. 3. an item of such knowledge or information. 4. Usually, instructions. orders or directions: The instructions are on the back of the box. 5. the act of furnishing with authoritative directions. 6. Computers. a command given […]
- Instruction scheduling
The compiler phase that orders instructions on a pipelined, superscalar, or VLIW architecture so as to maximise the number of function units operating in parallel and to minimise the time they spend waiting for each other. Examples are filling a delay slot; interspersing floating-point instructions with integer instructions to keep both units operating; making adjacent […]
- Instruction set
architecture The collection of machine language instructions that a particular processor understands. The term is almost synonymous with “instruction set architecture” since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate. (1999-07-05)
- Instruction set architecture
architecture (ISA) The parts of a processor’s design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation, such as number of superscalar functional units, cache size and cycle speed, are not part of the ISA. […]